Sergey Ostrikov

Hi, I’m a systems engineer with a decade of hands-on experience in silicon development, including early-stage development of an AI inference accelerator and full-cycle work on a secure memory IC from concept to delivery and certification. I enjoy building prototypes that help stakeholders decide on new product commitments. Some things I’ve been up to professionally:

Lead Principal Engineer, Infineon Technologies, 2020-2025, San Jose, CA

●	In this role, I shaped the evaluation of an analog in-memory compute technology. I developed a graph compiler as a primary vehicle for architecture exploration and tradeoff analysis.
●	For PPA analysis, I developed a heuristic-based algorithm that maps a task graph onto a hardware connectivity graph (demo). (neural network) → (distributed in-memory compute fabric)
●	Formulated a nuanced approach for assessing accuracy of analog inference beyond standard evaluation metrics (description).
●	And finally, I did a comparison of the technology against leading AI accelerators and presented my findings at a JEDEC AI workshop.

Conference Talks

●	Graph Compiler for a Weight-Stationary Dataflow JEDEC Mobile/Client/AI Computing Forum 🇺🇸 San Jose, CA, May 2024
●	In-memory Computing using SONOS (Non-Volatile Memory) JEDEC Mobile/Client/AI Computing Forum 🇹🇼 Hsinchu, Taiwan and 🇰🇷 Seoul, S. Korea , May 2023

●	Resilient Boot (secure boot on processors without eNVM) IEEE International Conference on Cyber Security and Resilience 💻 Virtual, July 2021

Systems Engineer, Cypress Semiconductor, 2014-2020, San Jose, CA

●	In this role, I led a feasibility study for a secure memory device, analyzed and improved secure memory IP, and contributed to successful security certification (CAVP, CMVP).
●	Wrote a C model of a secure NOR Flash device to determine security aspects of the product itself, along with the systems it was intended to operate within (available in the product SDK).
●	Coded apps, middleware and numerous drivers for demo purposes: MQTT, TLS, TCP/IP, WiFi, ETH, BLE, …

Publications

Resilient Boot

A practical guide for achieving FIPS-certifiable DICE attestation

Secure memories in a connected world (page 30)

How to design FIPS 140-2 cryptographic modules to meet TCG Implicit Identity Based Device Attestation

Patents

Memory device resilient to cyber-attacks and malfunction

Methods for updating firmware with single memory device

Secured communication from within non-volatile memory device

Access-aware flash translation layer on flash memory IC

Contributions to Standards

JEDEC: Serial NOR Security Hardware Abstraction Layer (throughout the doc)

TCG: DICE Attestation Architecture (chapter 7)

TCG: Cyber Resilient Module and Building Block Requirements (storage protection)